// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  cfg_disp_davinci_dvpp_reg_offset_field.h
// Project line  :  ICT
// Department    :  CAD Development Department
// Author        :  Huawei
// Version       :  V100
// Date          :  2016/7/1
// Description   :  The description of P680 project
// Others        :  Generated automatically by nManager V4.1 
// History       :  Huawei 2018/05/16 14:31:17 Create file
// ******************************************************************************

#ifndef __CFG_DISP_DAVINCI_DVPP_REG_OFFSET_FIELD_H__
#define __CFG_DISP_DAVINCI_DVPP_REG_OFFSET_FIELD_H__

#define CFG_DISP_DAVINCI_DVPP_BYPASS_ROUTE_LEN    8
#define CFG_DISP_DAVINCI_DVPP_BYPASS_ROUTE_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_BAR_DEF_ROUTE_RC0_LEN    8
#define CFG_DISP_DAVINCI_DVPP_BAR_DEF_ROUTE_RC0_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_BAR_DEF_ROUTE_RC1_LEN    8
#define CFG_DISP_DAVINCI_DVPP_BAR_DEF_ROUTE_RC1_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_ID_PA_LEN    7
#define CFG_DISP_DAVINCI_DVPP_ID_PA_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_ERR_RSP_DISABLE_PORT_SLAVE_LEN    8
#define CFG_DISP_DAVINCI_DVPP_ERR_RSP_DISABLE_PORT_SLAVE_OFFSET 8
#define CFG_DISP_DAVINCI_DVPP_ERR_RSP_DISABLE_DEF_SLAVE_LEN     1
#define CFG_DISP_DAVINCI_DVPP_ERR_RSP_DISABLE_DEF_SLAVE_OFFSET  0

#define CFG_DISP_DAVINCI_DVPP_EWA_MASK_LEN    1
#define CFG_DISP_DAVINCI_DVPP_EWA_MASK_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE_EN0_LEN    1
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE_EN0_OFFSET 8
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE0_LEN       6
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE0_OFFSET    0

#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE_EN1_LEN    1
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE_EN1_OFFSET 8
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE1_LEN       6
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE1_OFFSET    0

#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE_EN2_LEN    1
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE_EN2_OFFSET 8
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE2_LEN       6
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE2_OFFSET    0

#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE_EN3_LEN    1
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE_EN3_OFFSET 8
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE3_LEN       6
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE3_OFFSET    0

#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE_EN4_LEN    1
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE_EN4_OFFSET 8
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE4_LEN       6
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE4_OFFSET    0

#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE_EN5_LEN    1
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE_EN5_OFFSET 8
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE5_LEN       6
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE5_OFFSET    0

#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE_EN6_LEN    1
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE_EN6_OFFSET 8
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE6_LEN       6
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE6_OFFSET    0

#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE_EN7_LEN    1
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE_EN7_OFFSET 8
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE7_LEN       6
#define CFG_DISP_DAVINCI_DVPP_ORDER_ADDR_RANGE7_OFFSET    0

#define CFG_DISP_DAVINCI_DVPP_ECAM_FUNC_EN_LEN    1
#define CFG_DISP_DAVINCI_DVPP_ECAM_FUNC_EN_OFFSET 3
#define CFG_DISP_DAVINCI_DVPP_BAR_FUNC_EN_LEN     2
#define CFG_DISP_DAVINCI_DVPP_BAR_FUNC_EN_OFFSET  1
#define CFG_DISP_DAVINCI_DVPP_VF_FUNC_EN_LEN      1
#define CFG_DISP_DAVINCI_DVPP_VF_FUNC_EN_OFFSET   0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW_EN_LEN    12
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW_EN_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_BAR_RC0_DAW_EN_LEN    4
#define CFG_DISP_DAVINCI_DVPP_DISP_BAR_RC0_DAW_EN_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_BAR_RC1_DAW_EN_LEN    4
#define CFG_DISP_DAVINCI_DVPP_DISP_BAR_RC1_DAW_EN_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW_EN_LEN    8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW_EN_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF_EN_LEN    32
#define CFG_DISP_DAVINCI_DVPP_DISP_VF_EN_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_VF_BASE_ADDR_LEN    24
#define CFG_DISP_DAVINCI_DVPP_VF_BASE_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_ECAM_BASE_ADDR_LEN    20
#define CFG_DISP_DAVINCI_DVPP_ECAM_BASE_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW0_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW0_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW0_SIZE_LEN    5
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW0_SIZE_OFFSET 16
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW0_DID_LEN     3
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW0_DID_OFFSET  0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW1_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW1_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW1_SIZE_LEN    5
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW1_SIZE_OFFSET 16
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW1_DID_LEN     3
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW1_DID_OFFSET  0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW2_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW2_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW2_SIZE_LEN    5
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW2_SIZE_OFFSET 16
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW2_DID_LEN     3
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW2_DID_OFFSET  0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW3_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW3_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW3_SIZE_LEN    5
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW3_SIZE_OFFSET 16
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW3_DID_LEN     3
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW3_DID_OFFSET  0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW4_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW4_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW4_SIZE_LEN    5
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW4_SIZE_OFFSET 16
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW4_DID_LEN     3
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW4_DID_OFFSET  0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW5_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW5_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW5_SIZE_LEN    5
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW5_SIZE_OFFSET 16
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW5_DID_LEN     3
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW5_DID_OFFSET  0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW6_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW6_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW6_SIZE_LEN    5
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW6_SIZE_OFFSET 16
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW6_DID_LEN     3
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW6_DID_OFFSET  0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW7_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW7_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW7_SIZE_LEN    5
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW7_SIZE_OFFSET 16
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW7_DID_LEN     3
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW7_DID_OFFSET  0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW8_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW8_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW8_SIZE_LEN    5
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW8_SIZE_OFFSET 16
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW8_DID_LEN     3
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW8_DID_OFFSET  0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW9_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW9_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW9_SIZE_LEN    5
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW9_SIZE_OFFSET 16
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW9_DID_LEN     3
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW9_DID_OFFSET  0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW10_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW10_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW10_SIZE_LEN    5
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW10_SIZE_OFFSET 16
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW10_DID_LEN     3
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW10_DID_OFFSET  0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW11_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW11_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW11_SIZE_LEN    5
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW11_SIZE_OFFSET 16
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW11_DID_LEN     3
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW11_DID_OFFSET  0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF0_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF0_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF1_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF1_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF2_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF2_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF3_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF3_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF4_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF4_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF5_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF5_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF6_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF6_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF7_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF7_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF8_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF8_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF9_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF9_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF10_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF10_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF11_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF11_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF12_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF12_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF13_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF13_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF14_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF14_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF15_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF15_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF16_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF16_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF17_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF17_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF18_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF18_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF19_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF19_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF20_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF20_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF21_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF21_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF22_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF22_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF23_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF23_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF24_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF24_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF25_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF25_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF26_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF26_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF27_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF27_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF28_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF28_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF29_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF29_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF30_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF30_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VF31_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_VF31_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW_RC0_BASE_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW_RC0_BASE_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW_RC0_LIMIT_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW_RC0_LIMIT_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW_RC1_BASE_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW_RC1_BASE_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_DAW_RC1_LIMIT_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_DAW_RC1_LIMIT_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW0_BASE_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW0_BASE_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW0_LIMIT_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW0_LIMIT_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW0_DID_LEN        3
#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW0_DID_OFFSET     4
#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW0_DID_CFG_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW0_DID_CFG_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW1_BASE_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW1_BASE_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW1_LIMIT_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW1_LIMIT_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW1_DID_LEN        3
#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW1_DID_OFFSET     4
#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW1_DID_CFG_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW1_DID_CFG_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW2_BASE_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW2_BASE_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW2_LIMIT_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW2_LIMIT_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW2_DID_LEN        3
#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW2_DID_OFFSET     4
#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW2_DID_CFG_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW2_DID_CFG_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW3_BASE_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW3_BASE_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW3_LIMIT_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW3_LIMIT_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW3_DID_LEN        3
#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW3_DID_OFFSET     4
#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW3_DID_CFG_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_RC0_BAR_DAW3_DID_CFG_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW0_BASE_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW0_BASE_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW0_LIMIT_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW0_LIMIT_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW0_DID_LEN        3
#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW0_DID_OFFSET     4
#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW0_DID_CFG_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW0_DID_CFG_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW1_BASE_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW1_BASE_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW1_LIMIT_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW1_LIMIT_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW1_DID_LEN        3
#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW1_DID_OFFSET     4
#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW1_DID_CFG_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW1_DID_CFG_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW2_BASE_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW2_BASE_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW2_LIMIT_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW2_LIMIT_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW2_DID_LEN        3
#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW2_DID_OFFSET     4
#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW2_DID_CFG_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW2_DID_CFG_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW3_BASE_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW3_BASE_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW3_LIMIT_ADDR_LEN    28
#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW3_LIMIT_ADDR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW3_DID_LEN        3
#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW3_DID_OFFSET     4
#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW3_DID_CFG_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_RC1_BAR_DAW3_DID_CFG_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW0_SIZE_LEN           5
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW0_SIZE_OFFSET        16
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW0_PCIE_BUS_ID_LEN    8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW0_PCIE_BUS_ID_OFFSET 8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW0_PCIE_DEV_ID_LEN    8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW0_PCIE_DEV_ID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW0_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW0_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW1_SIZE_LEN           5
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW1_SIZE_OFFSET        16
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW1_PCIE_BUS_ID_LEN    8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW1_PCIE_BUS_ID_OFFSET 8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW1_PCIE_DEV_ID_LEN    8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW1_PCIE_DEV_ID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW1_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW1_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW2_SIZE_LEN           5
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW2_SIZE_OFFSET        16
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW2_PCIE_BUS_ID_LEN    8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW2_PCIE_BUS_ID_OFFSET 8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW2_PCIE_DEV_ID_LEN    8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW2_PCIE_DEV_ID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW2_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW2_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW3_SIZE_LEN           5
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW3_SIZE_OFFSET        16
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW3_PCIE_BUS_ID_LEN    8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW3_PCIE_BUS_ID_OFFSET 8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW3_PCIE_DEV_ID_LEN    8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW3_PCIE_DEV_ID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW3_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW3_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW4_SIZE_LEN           5
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW4_SIZE_OFFSET        16
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW4_PCIE_BUS_ID_LEN    8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW4_PCIE_BUS_ID_OFFSET 8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW4_PCIE_DEV_ID_LEN    8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW4_PCIE_DEV_ID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW4_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW4_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW5_SIZE_LEN           5
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW5_SIZE_OFFSET        16
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW5_PCIE_BUS_ID_LEN    8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW5_PCIE_BUS_ID_OFFSET 8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW5_PCIE_DEV_ID_LEN    8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW5_PCIE_DEV_ID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW5_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW5_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW6_SIZE_LEN           5
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW6_SIZE_OFFSET        16
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW6_PCIE_BUS_ID_LEN    8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW6_PCIE_BUS_ID_OFFSET 8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW6_PCIE_DEV_ID_LEN    8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW6_PCIE_DEV_ID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW6_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW6_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW7_SIZE_LEN           5
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW7_SIZE_OFFSET        16
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW7_PCIE_BUS_ID_LEN    8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW7_PCIE_BUS_ID_OFFSET 8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW7_PCIE_DEV_ID_LEN    8
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW7_PCIE_DEV_ID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW7_DID_LEN    3
#define CFG_DISP_DAVINCI_DVPP_DISP_ECAM_DAW7_DID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_MAGIC_WORD_LEN    32
#define CFG_DISP_DAVINCI_DVPP_DISP_MAGIC_WORD_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_INTRAW_ERR_LEN    1
#define CFG_DISP_DAVINCI_DVPP_INTRAW_ERR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_INTMASK_ERR_LEN    1
#define CFG_DISP_DAVINCI_DVPP_INTMASK_ERR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_INT_ERR_LEN    1
#define CFG_DISP_DAVINCI_DVPP_INT_ERR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_INT_CLR_ERR_LEN    1
#define CFG_DISP_DAVINCI_DVPP_INT_CLR_ERR_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_INTRAW_RCV_ERR_RSP_LEN    8
#define CFG_DISP_DAVINCI_DVPP_INTRAW_RCV_ERR_RSP_OFFSET 8
#define CFG_DISP_DAVINCI_DVPP_INTRAW_TRAP_RSP_LEN       1
#define CFG_DISP_DAVINCI_DVPP_INTRAW_TRAP_RSP_OFFSET    1
#define CFG_DISP_DAVINCI_DVPP_INTRAW_TRAP_CMD_LEN       1
#define CFG_DISP_DAVINCI_DVPP_INTRAW_TRAP_CMD_OFFSET    0

#define CFG_DISP_DAVINCI_DVPP_INTMASK_RCV_ERR_RSP_LEN    8
#define CFG_DISP_DAVINCI_DVPP_INTMASK_RCV_ERR_RSP_OFFSET 8
#define CFG_DISP_DAVINCI_DVPP_INTMASK_TRAP_RSP_LEN       1
#define CFG_DISP_DAVINCI_DVPP_INTMASK_TRAP_RSP_OFFSET    1
#define CFG_DISP_DAVINCI_DVPP_INTMASK_TRAP_CMD_LEN       1
#define CFG_DISP_DAVINCI_DVPP_INTMASK_TRAP_CMD_OFFSET    0

#define CFG_DISP_DAVINCI_DVPP_INT_RCV_ERR_RSP_LEN    8
#define CFG_DISP_DAVINCI_DVPP_INT_RCV_ERR_RSP_OFFSET 8
#define CFG_DISP_DAVINCI_DVPP_INT_TRAP_RSP_LEN       1
#define CFG_DISP_DAVINCI_DVPP_INT_TRAP_RSP_OFFSET    1
#define CFG_DISP_DAVINCI_DVPP_INT_TRAP_CMD_LEN       1
#define CFG_DISP_DAVINCI_DVPP_INT_TRAP_CMD_OFFSET    0

#define CFG_DISP_DAVINCI_DVPP_CLR_ERR_RSP_LEN    8
#define CFG_DISP_DAVINCI_DVPP_CLR_ERR_RSP_OFFSET 8

#define CFG_DISP_DAVINCI_DVPP_ERR_ADDR_LOW_LEN    32
#define CFG_DISP_DAVINCI_DVPP_ERR_ADDR_LOW_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_ERR_ADDR_HIGH_LEN    32
#define CFG_DISP_DAVINCI_DVPP_ERR_ADDR_HIGH_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_ERR_SRCID_LEN     9
#define CFG_DISP_DAVINCI_DVPP_ERR_SRCID_OFFSET  12
#define CFG_DISP_DAVINCI_DVPP_ERR_LPID_LEN      3
#define CFG_DISP_DAVINCI_DVPP_ERR_LPID_OFFSET   8
#define CFG_DISP_DAVINCI_DVPP_ERR_OPCODE_LEN    6
#define CFG_DISP_DAVINCI_DVPP_ERR_OPCODE_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_ERR_CMD_STATIC_REQ_IND_LEN    1
#define CFG_DISP_DAVINCI_DVPP_ERR_CMD_STATIC_REQ_IND_OFFSET 16
#define CFG_DISP_DAVINCI_DVPP_ERR_CMD_PCRDTYPE_LEN          8
#define CFG_DISP_DAVINCI_DVPP_ERR_CMD_PCRDTYPE_OFFSET       8
#define CFG_DISP_DAVINCI_DVPP_ERR_DAW_OVERLAP_INFO_LEN      8
#define CFG_DISP_DAVINCI_DVPP_ERR_DAW_OVERLAP_INFO_OFFSET   0

#define CFG_DISP_DAVINCI_DVPP_ERR_ACCESS_RST_SLAVE_PORT_LEN    1
#define CFG_DISP_DAVINCI_DVPP_ERR_ACCESS_RST_SLAVE_PORT_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_P0_INGRESS_QUEUE_BUSY_LEN    1
#define CFG_DISP_DAVINCI_DVPP_P0_INGRESS_QUEUE_BUSY_OFFSET 19
#define CFG_DISP_DAVINCI_DVPP_P0_LONG_PKT_RCV_LEN          1
#define CFG_DISP_DAVINCI_DVPP_P0_LONG_PKT_RCV_OFFSET       18
#define CFG_DISP_DAVINCI_DVPP_P0_GRANT_UNFINISH_LEN        1
#define CFG_DISP_DAVINCI_DVPP_P0_GRANT_UNFINISH_OFFSET     17
#define CFG_DISP_DAVINCI_DVPP_P0_RETRY_UNFINISH_LEN        1
#define CFG_DISP_DAVINCI_DVPP_P0_RETRY_UNFINISH_OFFSET     16
#define CFG_DISP_DAVINCI_DVPP_P0_AR_UNFINISH_CNT_LEN       8
#define CFG_DISP_DAVINCI_DVPP_P0_AR_UNFINISH_CNT_OFFSET    8
#define CFG_DISP_DAVINCI_DVPP_P0_AW_UNFINISH_CNT_LEN       8
#define CFG_DISP_DAVINCI_DVPP_P0_AW_UNFINISH_CNT_OFFSET    0

#define CFG_DISP_DAVINCI_DVPP_P1_INGRESS_QUEUE_BUSY_LEN    1
#define CFG_DISP_DAVINCI_DVPP_P1_INGRESS_QUEUE_BUSY_OFFSET 19
#define CFG_DISP_DAVINCI_DVPP_P1_LONG_PKT_RCV_LEN          1
#define CFG_DISP_DAVINCI_DVPP_P1_LONG_PKT_RCV_OFFSET       18
#define CFG_DISP_DAVINCI_DVPP_P1_GRANT_UNFINISH_LEN        1
#define CFG_DISP_DAVINCI_DVPP_P1_GRANT_UNFINISH_OFFSET     17
#define CFG_DISP_DAVINCI_DVPP_P1_RETRY_UNFINISH_LEN        1
#define CFG_DISP_DAVINCI_DVPP_P1_RETRY_UNFINISH_OFFSET     16
#define CFG_DISP_DAVINCI_DVPP_P1_AR_UNFINISH_CNT_LEN       8
#define CFG_DISP_DAVINCI_DVPP_P1_AR_UNFINISH_CNT_OFFSET    8
#define CFG_DISP_DAVINCI_DVPP_P1_AW_UNFINISH_CNT_LEN       8
#define CFG_DISP_DAVINCI_DVPP_P1_AW_UNFINISH_CNT_OFFSET    0

#define CFG_DISP_DAVINCI_DVPP_P2_INGRESS_QUEUE_BUSY_LEN    1
#define CFG_DISP_DAVINCI_DVPP_P2_INGRESS_QUEUE_BUSY_OFFSET 19
#define CFG_DISP_DAVINCI_DVPP_P2_LONG_PKT_RCV_LEN          1
#define CFG_DISP_DAVINCI_DVPP_P2_LONG_PKT_RCV_OFFSET       18
#define CFG_DISP_DAVINCI_DVPP_P2_GRANT_UNFINISH_LEN        1
#define CFG_DISP_DAVINCI_DVPP_P2_GRANT_UNFINISH_OFFSET     17
#define CFG_DISP_DAVINCI_DVPP_P2_RETRY_UNFINISH_LEN        1
#define CFG_DISP_DAVINCI_DVPP_P2_RETRY_UNFINISH_OFFSET     16
#define CFG_DISP_DAVINCI_DVPP_P2_AR_UNFINISH_CNT_LEN       8
#define CFG_DISP_DAVINCI_DVPP_P2_AR_UNFINISH_CNT_OFFSET    8
#define CFG_DISP_DAVINCI_DVPP_P2_AW_UNFINISH_CNT_LEN       8
#define CFG_DISP_DAVINCI_DVPP_P2_AW_UNFINISH_CNT_OFFSET    0

#define CFG_DISP_DAVINCI_DVPP_P3_INGRESS_QUEUE_BUSY_LEN    1
#define CFG_DISP_DAVINCI_DVPP_P3_INGRESS_QUEUE_BUSY_OFFSET 19
#define CFG_DISP_DAVINCI_DVPP_P3_LONG_PKT_RCV_LEN          1
#define CFG_DISP_DAVINCI_DVPP_P3_LONG_PKT_RCV_OFFSET       18
#define CFG_DISP_DAVINCI_DVPP_P3_GRANT_UNFINISH_LEN        1
#define CFG_DISP_DAVINCI_DVPP_P3_GRANT_UNFINISH_OFFSET     17
#define CFG_DISP_DAVINCI_DVPP_P3_RETRY_UNFINISH_LEN        1
#define CFG_DISP_DAVINCI_DVPP_P3_RETRY_UNFINISH_OFFSET     16
#define CFG_DISP_DAVINCI_DVPP_P3_AR_UNFINISH_CNT_LEN       8
#define CFG_DISP_DAVINCI_DVPP_P3_AR_UNFINISH_CNT_OFFSET    8
#define CFG_DISP_DAVINCI_DVPP_P3_AW_UNFINISH_CNT_LEN       8
#define CFG_DISP_DAVINCI_DVPP_P3_AW_UNFINISH_CNT_OFFSET    0

#define CFG_DISP_DAVINCI_DVPP_P4_INGRESS_QUEUE_BUSY_LEN    1
#define CFG_DISP_DAVINCI_DVPP_P4_INGRESS_QUEUE_BUSY_OFFSET 19
#define CFG_DISP_DAVINCI_DVPP_P4_LONG_PKT_RCV_LEN          1
#define CFG_DISP_DAVINCI_DVPP_P4_LONG_PKT_RCV_OFFSET       18
#define CFG_DISP_DAVINCI_DVPP_P4_GRANT_UNFINISH_LEN        1
#define CFG_DISP_DAVINCI_DVPP_P4_GRANT_UNFINISH_OFFSET     17
#define CFG_DISP_DAVINCI_DVPP_P4_RETRY_UNFINISH_LEN        1
#define CFG_DISP_DAVINCI_DVPP_P4_RETRY_UNFINISH_OFFSET     16
#define CFG_DISP_DAVINCI_DVPP_P4_AR_UNFINISH_CNT_LEN       8
#define CFG_DISP_DAVINCI_DVPP_P4_AR_UNFINISH_CNT_OFFSET    8
#define CFG_DISP_DAVINCI_DVPP_P4_AW_UNFINISH_CNT_LEN       8
#define CFG_DISP_DAVINCI_DVPP_P4_AW_UNFINISH_CNT_OFFSET    0

#define CFG_DISP_DAVINCI_DVPP_P5_INGRESS_QUEUE_BUSY_LEN    1
#define CFG_DISP_DAVINCI_DVPP_P5_INGRESS_QUEUE_BUSY_OFFSET 19
#define CFG_DISP_DAVINCI_DVPP_P5_LONG_PKT_RCV_LEN          1
#define CFG_DISP_DAVINCI_DVPP_P5_LONG_PKT_RCV_OFFSET       18
#define CFG_DISP_DAVINCI_DVPP_P5_GRANT_UNFINISH_LEN        1
#define CFG_DISP_DAVINCI_DVPP_P5_GRANT_UNFINISH_OFFSET     17
#define CFG_DISP_DAVINCI_DVPP_P5_RETRY_UNFINISH_LEN        1
#define CFG_DISP_DAVINCI_DVPP_P5_RETRY_UNFINISH_OFFSET     16
#define CFG_DISP_DAVINCI_DVPP_P5_AR_UNFINISH_CNT_LEN       8
#define CFG_DISP_DAVINCI_DVPP_P5_AR_UNFINISH_CNT_OFFSET    8
#define CFG_DISP_DAVINCI_DVPP_P5_AW_UNFINISH_CNT_LEN       8
#define CFG_DISP_DAVINCI_DVPP_P5_AW_UNFINISH_CNT_OFFSET    0

#define CFG_DISP_DAVINCI_DVPP_P6_INGRESS_QUEUE_BUSY_LEN    1
#define CFG_DISP_DAVINCI_DVPP_P6_INGRESS_QUEUE_BUSY_OFFSET 19
#define CFG_DISP_DAVINCI_DVPP_P6_LONG_PKT_RCV_LEN          1
#define CFG_DISP_DAVINCI_DVPP_P6_LONG_PKT_RCV_OFFSET       18
#define CFG_DISP_DAVINCI_DVPP_P6_GRANT_UNFINISH_LEN        1
#define CFG_DISP_DAVINCI_DVPP_P6_GRANT_UNFINISH_OFFSET     17
#define CFG_DISP_DAVINCI_DVPP_P6_RETRY_UNFINISH_LEN        1
#define CFG_DISP_DAVINCI_DVPP_P6_RETRY_UNFINISH_OFFSET     16
#define CFG_DISP_DAVINCI_DVPP_P6_AR_UNFINISH_CNT_LEN       8
#define CFG_DISP_DAVINCI_DVPP_P6_AR_UNFINISH_CNT_OFFSET    8
#define CFG_DISP_DAVINCI_DVPP_P6_AW_UNFINISH_CNT_LEN       8
#define CFG_DISP_DAVINCI_DVPP_P6_AW_UNFINISH_CNT_OFFSET    0

#define CFG_DISP_DAVINCI_DVPP_P7_INGRESS_QUEUE_BUSY_LEN    1
#define CFG_DISP_DAVINCI_DVPP_P7_INGRESS_QUEUE_BUSY_OFFSET 19
#define CFG_DISP_DAVINCI_DVPP_P7_LONG_PKT_RCV_LEN          1
#define CFG_DISP_DAVINCI_DVPP_P7_LONG_PKT_RCV_OFFSET       18
#define CFG_DISP_DAVINCI_DVPP_P7_GRANT_UNFINISH_LEN        1
#define CFG_DISP_DAVINCI_DVPP_P7_GRANT_UNFINISH_OFFSET     17
#define CFG_DISP_DAVINCI_DVPP_P7_RETRY_UNFINISH_LEN        1
#define CFG_DISP_DAVINCI_DVPP_P7_RETRY_UNFINISH_OFFSET     16
#define CFG_DISP_DAVINCI_DVPP_P7_AR_UNFINISH_CNT_LEN       8
#define CFG_DISP_DAVINCI_DVPP_P7_AR_UNFINISH_CNT_OFFSET    8
#define CFG_DISP_DAVINCI_DVPP_P7_AW_UNFINISH_CNT_LEN       8
#define CFG_DISP_DAVINCI_DVPP_P7_AW_UNFINISH_CNT_OFFSET    0

#define CFG_DISP_DAVINCI_DVPP_DEF_INGRESS_QUEUE_BUSY_LEN    1
#define CFG_DISP_DAVINCI_DVPP_DEF_INGRESS_QUEUE_BUSY_OFFSET 19
#define CFG_DISP_DAVINCI_DVPP_DEF_LONG_PKT_RCV_LEN          1
#define CFG_DISP_DAVINCI_DVPP_DEF_LONG_PKT_RCV_OFFSET       18
#define CFG_DISP_DAVINCI_DVPP_DEF_GRANT_UNFINISH_LEN        1
#define CFG_DISP_DAVINCI_DVPP_DEF_GRANT_UNFINISH_OFFSET     17
#define CFG_DISP_DAVINCI_DVPP_DEF_RETRY_UNFINISH_LEN        1
#define CFG_DISP_DAVINCI_DVPP_DEF_RETRY_UNFINISH_OFFSET     16
#define CFG_DISP_DAVINCI_DVPP_DEF_CMD_UNFINISH_CNT_LEN      8
#define CFG_DISP_DAVINCI_DVPP_DEF_CMD_UNFINISH_CNT_OFFSET   0

#define CFG_DISP_DAVINCI_DVPP_BARRIER_CNT_LEN    5
#define CFG_DISP_DAVINCI_DVPP_BARRIER_CNT_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_ECO_CFG0_LEN    32
#define CFG_DISP_DAVINCI_DVPP_DISP_ECO_CFG0_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_ECO_CFG1_LEN    32
#define CFG_DISP_DAVINCI_DVPP_DISP_ECO_CFG1_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_ECO_CFG2_LEN    32
#define CFG_DISP_DAVINCI_DVPP_DISP_ECO_CFG2_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_ECO_CFG3_LEN    32
#define CFG_DISP_DAVINCI_DVPP_DISP_ECO_CFG3_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_DISP_VERSION_ID_LEN    32
#define CFG_DISP_DAVINCI_DVPP_DISP_VERSION_ID_OFFSET 0







#define CFG_DISP_DAVINCI_DVPP_DISP_BUSY_RXREQ_BARRIER_LEN    1
#define CFG_DISP_DAVINCI_DVPP_DISP_BUSY_RXREQ_BARRIER_OFFSET 10
#define CFG_DISP_DAVINCI_DVPP_DISP_BUSY_RXREQ_QUEUE_LEN      1
#define CFG_DISP_DAVINCI_DVPP_DISP_BUSY_RXREQ_QUEUE_OFFSET   9
#define CFG_DISP_DAVINCI_DVPP_DISP_BUSY_SLV_DEF_LEN          1
#define CFG_DISP_DAVINCI_DVPP_DISP_BUSY_SLV_DEF_OFFSET       8
#define CFG_DISP_DAVINCI_DVPP_DISP_BUSY_SLV_PORT_LEN         8
#define CFG_DISP_DAVINCI_DVPP_DISP_BUSY_SLV_PORT_OFFSET      0

#define CFG_DISP_DAVINCI_DVPP_DISP_DFX_ICG_EN_LEN    1
#define CFG_DISP_DAVINCI_DVPP_DISP_DFX_ICG_EN_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_TRAP_PORT_RW_LEN     1
#define CFG_DISP_DAVINCI_DVPP_TRAP_PORT_RW_OFFSET  8
#define CFG_DISP_DAVINCI_DVPP_TRAP_PORT_SEL_LEN    8
#define CFG_DISP_DAVINCI_DVPP_TRAP_PORT_SEL_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_TRAP_EN_RSP_LEN    1
#define CFG_DISP_DAVINCI_DVPP_TRAP_EN_RSP_OFFSET 1
#define CFG_DISP_DAVINCI_DVPP_TRAP_EN_CMD_LEN    1
#define CFG_DISP_DAVINCI_DVPP_TRAP_EN_CMD_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_TRAP_REVERSE_RSP_LEN    1
#define CFG_DISP_DAVINCI_DVPP_TRAP_REVERSE_RSP_OFFSET 1
#define CFG_DISP_DAVINCI_DVPP_TRAP_REVERSE_CMD_LEN    1
#define CFG_DISP_DAVINCI_DVPP_TRAP_REVERSE_CMD_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_TRAP_ORDER_RSP_LEN    1
#define CFG_DISP_DAVINCI_DVPP_TRAP_ORDER_RSP_OFFSET 1
#define CFG_DISP_DAVINCI_DVPP_TRAP_ORDER_CMD_LEN    1
#define CFG_DISP_DAVINCI_DVPP_TRAP_ORDER_CMD_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_COMP_AW_ADDR_LOW_LEN    32
#define CFG_DISP_DAVINCI_DVPP_COMP_AW_ADDR_LOW_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_COMP_AW_ADDR_HIGH_LEN    16
#define CFG_DISP_DAVINCI_DVPP_COMP_AW_ADDR_HIGH_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_MASK_AW_ADDR_LOW_LEN    32
#define CFG_DISP_DAVINCI_DVPP_MASK_AW_ADDR_LOW_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_MASK_AW_ADDR_HIGH_LEN    16
#define CFG_DISP_DAVINCI_DVPP_MASK_AW_ADDR_HIGH_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_COMP_CMD_SRCID_LEN    9
#define CFG_DISP_DAVINCI_DVPP_COMP_CMD_SRCID_OFFSET 8
#define CFG_DISP_DAVINCI_DVPP_COMP_CMD_LPID_LEN     3
#define CFG_DISP_DAVINCI_DVPP_COMP_CMD_LPID_OFFSET  0

#define CFG_DISP_DAVINCI_DVPP_MASK_CMD_SRCID_LEN    9
#define CFG_DISP_DAVINCI_DVPP_MASK_CMD_SRCID_OFFSET 8
#define CFG_DISP_DAVINCI_DVPP_MASK_CMD_LPID_LEN     3
#define CFG_DISP_DAVINCI_DVPP_MASK_CMD_LPID_OFFSET  0

#define CFG_DISP_DAVINCI_DVPP_COMP_RSP_SRCID_LEN    9
#define CFG_DISP_DAVINCI_DVPP_COMP_RSP_SRCID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_MASK_RSP_SRCID_LEN    9
#define CFG_DISP_DAVINCI_DVPP_MASK_RSP_SRCID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_SRAM_PORT_EN_LEN        8
#define CFG_DISP_DAVINCI_DVPP_SRAM_PORT_EN_OFFSET     3
#define CFG_DISP_DAVINCI_DVPP_CACHEABLE_WNS_EN_LEN    1
#define CFG_DISP_DAVINCI_DVPP_CACHEABLE_WNS_EN_OFFSET 2
#define CFG_DISP_DAVINCI_DVPP_VALID_SHADOW_EN_LEN     1
#define CFG_DISP_DAVINCI_DVPP_VALID_SHADOW_EN_OFFSET  1
#define CFG_DISP_DAVINCI_DVPP_BAR_PATH_SEL_LEN        1
#define CFG_DISP_DAVINCI_DVPP_BAR_PATH_SEL_OFFSET     0

#define CFG_DISP_DAVINCI_DVPP_TRAP_INFO_CMD_ADDR_H_LEN    16
#define CFG_DISP_DAVINCI_DVPP_TRAP_INFO_CMD_ADDR_H_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_TRAP_INFO_CMD_LEN_LEN      6
#define CFG_DISP_DAVINCI_DVPP_TRAP_INFO_CMD_LEN_OFFSET   20
#define CFG_DISP_DAVINCI_DVPP_TRAP_INFO_CMD_SIZE_LEN     3
#define CFG_DISP_DAVINCI_DVPP_TRAP_INFO_CMD_SIZE_OFFSET  16
#define CFG_DISP_DAVINCI_DVPP_TRAP_INFO_CMD_LPID_LEN     3
#define CFG_DISP_DAVINCI_DVPP_TRAP_INFO_CMD_LPID_OFFSET  12
#define CFG_DISP_DAVINCI_DVPP_TRAP_INFO_CMD_SRCID_LEN    9
#define CFG_DISP_DAVINCI_DVPP_TRAP_INFO_CMD_SRCID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_TRAP_INFO_RSP_SRCID_LEN    9
#define CFG_DISP_DAVINCI_DVPP_TRAP_INFO_RSP_SRCID_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_P0_CUR_ADDR_L_LEN    32
#define CFG_DISP_DAVINCI_DVPP_P0_CUR_ADDR_L_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_P0_CUR_ADDR_H_LEN    32
#define CFG_DISP_DAVINCI_DVPP_P0_CUR_ADDR_H_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_P0_CUR_RW_IND_LEN    2
#define CFG_DISP_DAVINCI_DVPP_P0_CUR_RW_IND_OFFSET 16
#define CFG_DISP_DAVINCI_DVPP_P0_CUR_SRCID_LEN     9
#define CFG_DISP_DAVINCI_DVPP_P0_CUR_SRCID_OFFSET  4
#define CFG_DISP_DAVINCI_DVPP_P0_CUR_LPID_LEN      3
#define CFG_DISP_DAVINCI_DVPP_P0_CUR_LPID_OFFSET   0

#define CFG_DISP_DAVINCI_DVPP_P1_CUR_ADDR_L_LEN    32
#define CFG_DISP_DAVINCI_DVPP_P1_CUR_ADDR_L_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_P1_CUR_ADDR_H_LEN    32
#define CFG_DISP_DAVINCI_DVPP_P1_CUR_ADDR_H_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_P1_CUR_RW_IND_LEN    2
#define CFG_DISP_DAVINCI_DVPP_P1_CUR_RW_IND_OFFSET 16
#define CFG_DISP_DAVINCI_DVPP_P1_CUR_SRCID_LEN     9
#define CFG_DISP_DAVINCI_DVPP_P1_CUR_SRCID_OFFSET  4
#define CFG_DISP_DAVINCI_DVPP_P1_CUR_LPID_LEN      3
#define CFG_DISP_DAVINCI_DVPP_P1_CUR_LPID_OFFSET   0

#define CFG_DISP_DAVINCI_DVPP_P2_CUR_ADDR_L_LEN    32
#define CFG_DISP_DAVINCI_DVPP_P2_CUR_ADDR_L_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_P2_CUR_ADDR_H_LEN    32
#define CFG_DISP_DAVINCI_DVPP_P2_CUR_ADDR_H_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_P2_CUR_RW_IND_LEN    2
#define CFG_DISP_DAVINCI_DVPP_P2_CUR_RW_IND_OFFSET 16
#define CFG_DISP_DAVINCI_DVPP_P2_CUR_SRCID_LEN     9
#define CFG_DISP_DAVINCI_DVPP_P2_CUR_SRCID_OFFSET  4
#define CFG_DISP_DAVINCI_DVPP_P2_CUR_LPID_LEN      3
#define CFG_DISP_DAVINCI_DVPP_P2_CUR_LPID_OFFSET   0

#define CFG_DISP_DAVINCI_DVPP_P3_CUR_ADDR_L_LEN    32
#define CFG_DISP_DAVINCI_DVPP_P3_CUR_ADDR_L_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_P3_CUR_ADDR_H_LEN    32
#define CFG_DISP_DAVINCI_DVPP_P3_CUR_ADDR_H_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_P3_CUR_RW_IND_LEN    2
#define CFG_DISP_DAVINCI_DVPP_P3_CUR_RW_IND_OFFSET 16
#define CFG_DISP_DAVINCI_DVPP_P3_CUR_SRCID_LEN     9
#define CFG_DISP_DAVINCI_DVPP_P3_CUR_SRCID_OFFSET  4
#define CFG_DISP_DAVINCI_DVPP_P3_CUR_LPID_LEN      3
#define CFG_DISP_DAVINCI_DVPP_P3_CUR_LPID_OFFSET   0

#define CFG_DISP_DAVINCI_DVPP_P4_CUR_ADDR_L_LEN    32
#define CFG_DISP_DAVINCI_DVPP_P4_CUR_ADDR_L_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_P4_CUR_ADDR_H_LEN    32
#define CFG_DISP_DAVINCI_DVPP_P4_CUR_ADDR_H_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_P4_CUR_RW_IND_LEN    2
#define CFG_DISP_DAVINCI_DVPP_P4_CUR_RW_IND_OFFSET 16
#define CFG_DISP_DAVINCI_DVPP_P4_CUR_SRCID_LEN     9
#define CFG_DISP_DAVINCI_DVPP_P4_CUR_SRCID_OFFSET  4
#define CFG_DISP_DAVINCI_DVPP_P4_CUR_LPID_LEN      3
#define CFG_DISP_DAVINCI_DVPP_P4_CUR_LPID_OFFSET   0

#define CFG_DISP_DAVINCI_DVPP_P5_CUR_ADDR_L_LEN    32
#define CFG_DISP_DAVINCI_DVPP_P5_CUR_ADDR_L_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_P5_CUR_ADDR_H_LEN    32
#define CFG_DISP_DAVINCI_DVPP_P5_CUR_ADDR_H_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_P5_CUR_RW_IND_LEN    2
#define CFG_DISP_DAVINCI_DVPP_P5_CUR_RW_IND_OFFSET 16
#define CFG_DISP_DAVINCI_DVPP_P5_CUR_SRCID_LEN     9
#define CFG_DISP_DAVINCI_DVPP_P5_CUR_SRCID_OFFSET  4
#define CFG_DISP_DAVINCI_DVPP_P5_CUR_LPID_LEN      3
#define CFG_DISP_DAVINCI_DVPP_P5_CUR_LPID_OFFSET   0

#define CFG_DISP_DAVINCI_DVPP_P6_CUR_ADDR_L_LEN    32
#define CFG_DISP_DAVINCI_DVPP_P6_CUR_ADDR_L_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_P6_CUR_ADDR_H_LEN    32
#define CFG_DISP_DAVINCI_DVPP_P6_CUR_ADDR_H_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_P6_CUR_RW_IND_LEN    2
#define CFG_DISP_DAVINCI_DVPP_P6_CUR_RW_IND_OFFSET 16
#define CFG_DISP_DAVINCI_DVPP_P6_CUR_SRCID_LEN     9
#define CFG_DISP_DAVINCI_DVPP_P6_CUR_SRCID_OFFSET  4
#define CFG_DISP_DAVINCI_DVPP_P6_CUR_LPID_LEN      3
#define CFG_DISP_DAVINCI_DVPP_P6_CUR_LPID_OFFSET   0

#define CFG_DISP_DAVINCI_DVPP_P7_CUR_ADDR_L_LEN    32
#define CFG_DISP_DAVINCI_DVPP_P7_CUR_ADDR_L_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_P7_CUR_ADDR_H_LEN    32
#define CFG_DISP_DAVINCI_DVPP_P7_CUR_ADDR_H_OFFSET 0

#define CFG_DISP_DAVINCI_DVPP_P7_CUR_RW_IND_LEN    2
#define CFG_DISP_DAVINCI_DVPP_P7_CUR_RW_IND_OFFSET 16
#define CFG_DISP_DAVINCI_DVPP_P7_CUR_SRCID_LEN     9
#define CFG_DISP_DAVINCI_DVPP_P7_CUR_SRCID_OFFSET  4
#define CFG_DISP_DAVINCI_DVPP_P7_CUR_LPID_LEN      3
#define CFG_DISP_DAVINCI_DVPP_P7_CUR_LPID_OFFSET   0

#endif // __CFG_DISP_DAVINCI_DVPP_REG_OFFSET_FIELD_H__
